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Digital-to-analog converter (DAC)
RM0008
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.
12.4.11
Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
●
●
●
●
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
12.5
12.5.1
DAC registers
DAC control register (DAC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DMA
EN2
MAMP2[3:0]
WAVE2[1:0]
TSEL2[2:0]
TEN2
BOFF2
EN2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DMA
EN1
MAMP1[3:0]
WAVE1[1:0]
TSEL1[2:0]
TEN1
BOFF1
EN1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:29 Reserved.
Bit 28 DMAEN2 : DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
244/995
Doc ID 13902 Rev 9
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